1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the same.
2. Background Art
A technique for three-dimensionally arranging memory cells is proposed in, for instance, JP-A-2007-266143(Kokai). In this technique, a plurality of conductive layers, each functioning as a word electrode or control gate in a memory device, and dielectric layers are alternately stacked into a stacked structure. Through holes (memory holes) are formed in the stacked structure, and a charge storage layer is formed on the inner wall of the hole, in which silicon is subsequently buried in a columnar shape.
Furthermore, in the technique disclosed in JP-A-2007-266143(Kokai), the end portions of the conductive layers are formed into a staircase shape, and its step differences are used to form contact holes for connecting upper interconnects to the respective conductive layers by the same etching process.
Each contact hole has a different depth depending on the depth position of the corresponding conductive layer. Here, simultaneous etching of the contact holes different in depth is likely to cause variation in the etching amount (etching depth) of each conductive layer reached by the bottom of the corresponding contact hole. Variation in the etching amount of each conductive layer results in variation in the area of contact with the contact electrode buried in the contact hole. Consequently, contact resistance to the contact electrode is varied between the conductive layers.